//------------------------------------------------
// regfile.v
//
// James Forrest, 2013
// Based on code by:
// David_Harris@hmc.edu 3 November 2005
//
// Pipelined MIPS processor
//------------------------------------------------

module regfile(input         clk,
               input         we3, 
               input  [4:0]  ra1, ra2, wa3, 
               input  [31:0] wd3, 
               output [31:0] rd1, rd2,
               input   [4:0] debugAddress,
               inout  [31:0] debugData
			   );

  reg [31:0] rf[31:0];
  
  // three ported register file
  // read two ports combinationally
  // write third port on falling edge of clock
  // register 0 hardwired to 0

  // synchronous reset to zeros

  always @(negedge clk) begin
    if (we3) rf[wa3] <= wd3;
  end

  assign #1 rd1 = (ra1 != 0) ? rf[ra1] : 0;
  assign #1 rd2 = (ra2 != 0) ? rf[ra2] : 0;
  // this port is read-write for pc debug, exposed by the cpu, not sure if this will allow write
  assign #1 debugData = (debugAddress != 0) ? rf[debugAddress] : 0;
endmodule
